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FX806A a udio p rocessor serial clock main process out xtal/clock clock generator de-emphasis filter (rx) audio in input process main process output drives to external audio processes external audio process in calibration input attenuator chip select primary and secondary audio inputs voice. sub-/audio tone. ffsk. etc. sum out mod. in command data # # # (tx) mic. in attenuator modulation 2 out modulation 1 out loudspeaker audio transmitter modulation drives c-bus interface vogad sense attenuator modulation summing amp power supply pre-emphasis limiting filtering gain setting # indicates logic control # # # # # # # # # mic. & vogad amps low & highpass filters gain set vogad sense # # buffer vogad sense xtal fig.1 FX806A audio processor l main process conditioning for input or external process signals with gain/pre-emphasis, high and lowpass switched capacitor filters and a transmitter deviation limiter. the main process output may be switched to v bias . l summation and output drives main voice audio from the main process is combined with signalling and data from other dbs 800 facilities, to provide the composite (in and outband) signal for the digitally adjustable transmitter modulation drives. received audio is level (volume) adjusted for output to loudspeaker circuitry. signal-level stability and therefore output accuracy, of the FX806A is maintained by a voltage-controlled gain system (vogad) with specific gain sensors that are selected automatically by the internal/external mode command. the vogad system permits high deviation with low distortion. this is achieved by reducing the path gain (and so reducing the distortion introduced by the peak deviation limiter) when the input signal is large. signal levels can be controlled to provide dynamic- compensation for such factors as temperature drift, vco non-linearity, etc. FX806A audio output stages can be completely disabled or the whole microcircuit placed into a powersave mode, leaving only clock and c-bus circuitry active. the FX806A is a low-power, 5-volt cmos integrated circuit and is available in 24-pin dil cerdip and 24-pin/lead plastic smd packages. brief description intended primarily to operate as the audio terminal of radio systems using the dbs 800 digitally-integrated baseband system, the FX806A is a pmr audio processor which meets eia and cept audio specifications. using a unique filter line-up, the FX806A offers lower distortion versus modulation level figures than conventional filter/limiter configurations. the FX806A is a half-duplex device whose signal paths and level-setting elements are dynamically configured and adjusted by digital information sent from the radio m controller using c-bus hardware and software protocol. figure 5 shows a complete functional block diagram of the FX806A signal paths which can be viewed as 3 sections: l input process selectable transmit or receive input paths. the transmit path with low-noise input and vogad amplifiers and bandpass filtered stages provides good signal- to-noise performance at low input levels and minimum distortion for high-drive modulation signals. de-emphasis is software selectable at the rx audio input for fm or pm radio configurations. this initial audio, after in-line gain adjustment, is available for switching to either external audio processes (such as scrambling) or internally to the main process stages. publication d/806a/3 july 1994
2 pin number function FX806A j/lg/ls 1 2 3 4 5 6 7 8 9 10 11 12 xtal: the output of the on-chip clock oscillator. external components are required at this output when a xtal circuit is employed. see figure 2, inset 2. xtal/clock : the input to the on-chip clock oscillator inverter. a xtal or externally derived clock should be connected here. see figure 2, inset 2. this clock provides timing for on-chip elements, filters etc. serial clock: the c-bus, serial data loading clock input. this clock, produced by the m controller, is used for transfer timing of command data to the audio processor. see timing diagrams and system support document. command data: the c-bus, serial data input from the m controller. command data is loaded to this device in 8-bit bytes, msb (b7) first, and lsb (b0) last, synchronized to the serial clock. the command/data instruction is acted upon at the end of loading the whole instruction. command information is detailed in tables 1, 2, 3, 4 and 5. see timing diagrams and system support document. chip select (cs): the c-bus, data loading control function. this input is provided by the m controller. command data transfer sequences are initiated, completed or aborted by the cs signal. see timing diagrams and system support document. vogad out: the output of the relevant vogad sensor. this output, with external attack and decay setting components, should be connected as in figures 2 and 3, to the vogad in pin. rx audio in: the audio input to the FX806A from the radio receiver's demodulator circuits. this input, which requires to be a.c. coupled with capacitor c 12 , is selected by a control command bit. vogad in: the gain control signal from the selected vogad sensor (vogad out) to the input process voltage controlled amplifier. vogad operation is enabled via a mode command (bit5). individual sensors, automatically selected, permit gain control from either the input process or an external process. external attack and decay setting components should be applied as recommended in figures 2 and 3. v bias : the output of the on-chip analogue circuitry bias system, held internally at v dd /2. this pin should be decoupled to v ss by a capacitor c 10 , see figure 2. mic in (+): the non-inverting input to the microphone op-amp. this input requires external components for op-amp gain/attenuation setting as shown in figure 2, inset 1. mic in (C): the inverting input to the microphone op-amp. this input requires external components for op-amp gain/attenuation setting as shown in figure 2, inset 1. v ss : negative supply rail (gnd).
3 pin number function FX806A j/lg/ls 13 14 15 16 17 18 19 20 21 22 23 24 mic out: the output of the microphone op-amp, used with the mic in (C) input to provide the required gain/attenuation using external components as shown in figure 2. the external components shown are to assist in the use of this amplifier with either inverting or non-inverting inputs. during powersave (volume command) this output is placed at v ss . processed audio in: the input to the device from such external audio processes as voice store and retrieve or frequency domain scrambling. this input, which requires to be a.c. coupled with a capacitor, c 13 , is selected by a mode command bit. external audio process: the buffered output of the input processing stage. for further external audio processing prior to re-introduction at the processed audio in pin. calibration input: a unique input, intended to be used for dynamic balancing of the modulator drives and for measuring deviation limiter levels. a cue (beep) input from the fx803 audio tone processor can be entered on this line. this input is selected via a mode command bit (11 h ) and is self-biased. main process out: the output of the main process stage. this output is summed with additional system inputs as required (audio, sub-audio signalling, ffsk C see system overview) in the on-chip modulation summing amplifier. external components as shown in figure 2 should be used as required. sum in: the input and output terminals of the on-chip modulation summing amplifier. external components are required for input signals, with gain/attenuation setting as shown in figure 2. for single-signal, no-gain requirements, main process out may be linked directly to modulation in. sum out: modulation in: the final, composite modulating signal to vco (mod 1) and reference (mod 2) output drives. audio output: the processed audio signal output intended as a received audio (volume) output. though normally used in the rx mode, operation in tx is permitted. the output level of this attenuator is controlled via a volume set command. during powersave this output is placed at v ss . modulation 1 drive: the drive to the radio modulator voltage controlled oscillator (vco), from the composite audio summing stage. modulation 2 drive: the drive to the radio modulator reference oscillator, from the composite audio summing stage. note: these vco output attenuators are individually adjustable using the modulator levels command. during powersave these outputs are placed at v ss . v dd : positive supply rail. a single, stable +5 volt supply is required. levels and voltages within the audio processor are dependant upon this supply.
4 analogue application information external components main processout xtal/clock c 9 vogad out vogad in mic. in (+) mic. in (-) serial clock command data chip select rx audio in mic. out processed audio in external audio process calibration in sum in sum out mod in audio out modulation 1 drive modulation 2 drive external signal and data inputs c 8 c 10 r 5 c 12 see inset 2 see inset 1 r 8 r 7 r 9 r 10 c 13 inset 2 xtal/clock c 7 x 1 1 2 FX806A j inset 1 mic. in (+) mic. in (-) mic. out 10 11 13 + - r 3 c 3 c 1 r 1 c 2 r 2 c 4 c 5 r 4 FX806A j xtal r 12 v ss v dd xtal v bias v ss v ss r 11 v ss v ss c 6 v bias c 11 v dd 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 FX806A j r 6 fig.2 recommended external components component value r 1 = 10.0k w r 2 10.0k w r 3 20.0k w r 4 20.0k w r 5 10.0k w r 6 2.2m w r 7 100k w r 8 100k w r 9 100k w r 10 = 100k w r 11 100k w r 12 2.2m w c 1 470nf c 2 470nf c 3 270pf c 4 270pf c 5 0.1 m f c 6 33pf c 7 = 5 C 65pf c 8 1.0 m f c 9 1.0 m f c 10 1.0 m f c 11 22pf c 12 100nf c 13 10.0nf x 13 4.0mhz tolerance: r = 10%. c = 20% notes to demonstrate the versatility of the mic. inputs, input op-amp gain/attenuation components for a voltage gain of 6.0db are shown (inset 1) in a differential configuration. components for a single (+ or -) input may be employed. resistor values r 7 to r 11 (summation components) are dependant upon application and configuration requirements. xtal circuit capacitors c 6 (c d ) and c 7 (c g ) shown (inset 2) are recommended in accordance with cml application note d/xt/2 december 1991 . circuit drive and drain resistors are incorporated on-chip. operation of any cml microcircuit without a xtal or clock input may cause device damage. to minimise damage in the event of a xtal/drive failure, it is recommended that the power rail (v dd ) is fitted with a current limiting device (resistor or fast reaction fuse). vogad components calculations C figures 2 and 3 provided r 5 >>1.0k w and r 6 = r 12 >>r 5 then: attack time (t a ) = r 5 x c 8 decay time (t d ) = r 6 x c 8 2
5 analogue application information ...... vogad in mic. in mic. in voltage controlled (vogad) amplifier processed audio in tx input process to external audio processes 5 r 6 r 12 r 8 c external integration components mic. out main process cal input vogad out tx drives rx drive ss v dd v hi/lo peak detector tx hi peak detector the gain control system tx calibration : from mic. in to modulator drives out disable peak detectors (mode command). set transmitter drives to 0db (mod levels set). pre-emphasis may be employed as required (control command). set input level amp to 0db (control command). (1) mic. in = 250mvrms at 1khz; set process gain amp for output of 1440mv p - p (100% deviation). (2) with process gain amp set as (1); mic in = 25mvrms at 1khz, set input level amp for output level of 308 mvrms (60% deviation). rx calibration: from rx audio in to audio output set audio output drive to 0db (volume set). leave process gain amp set as in (1) (above). (3) with rx audio in level of between 154mvrms and 308mvrms (see specification page), at 1khz, set the input level amp for an output level of 308mvrms. fig.3 vogad sensors and timing components C (part of fig.4) tx gain control of the FX806A is by 1 of 2 selectable signal peak detectors whose output is fed via external integrating components to the voltage controlled amplifier positioned in the tx input process path. the integrated level to the vogad in pin causes the voltage controlled amplifier gain to be reduced. vogad attack and decay calculations are described at the foot of the proceeding page. the FX806A automatically chooses the appropriate peak detector when the signal path is set by a mode command. the hi/lo peak detector is employed when external audio processes are used. the hi peak detector is employed when external audio processes are not used. suggested calibration methods to effectively null all internal microcircuit tolerances, the following initial calibration routine is suggested: fig.4 distortion vs mic. input level 0.2 0.4 0.6 mic. input level (vp-p) output distortion (%) limiter only hi-peak vogad & limiter 0.0 0 5 10 15 20 25 +10.0 0.0 +20.0 input level (db) 60% output deviation 308mvrms 0.071 internal path with pre-emphasis circuit elements set to 0db input level for 0db = 71.0mv p-p input frequency = 1.0khz output deviation = 60% = 0db
6 plmr audio processor explanatory block diagram fig.5 plmr audio processor C facilities notes main process deviation limiter process gain amp modulation summing amplifier output drives calibration input external audio process xtal/clock serial clock command data process l.p.f. process l.p.f. +3db to -4db vogad out vogad in external signal/data inputs main process out sum in sum out modulation in transmitter modulator drives mic. in mic. in input process input level amp de-emphasis mic. op-amp mic. out input h.p.f. tx rx +10db to -4db rx (demod) audio in processed audio in v dd v ss #c0 - 3 tx rx #m0 - 2 # = controlling logic bit c = control command m = mode command 0db level = 308mvrms (60% deviation) . d0 = mod 2 d1 = mod 1 v = volume set input select #c6 (enable) external signal mixing external integration components xtal tx 0db to -12.4db mod 1 db db #d(1) 0-4 db db 0db to -6.2db #d(0) 0-4 audio output 0db to -48.0db db db #v0 - 4 #c7 (enable) mod 2 0db 0db 0db @ 1khz gain set by external components # buffer amp c-bus interface and control logic # # vogad amp 0db input l.p.f. 0db -6db/oct h.p.f. v bias +6db/oct 0db 0db v bias clock generator chip select -24db to 6db v bias #c4 #m4 v bias v bias v bias #m6 on off #m3 #c5 #m7 #m3 hi-peak detector +ve peaks hi/lo-peak detector +ve & -ve peaks #v6 0db pre-emphasis 10db @ 1khz 0db h.p.f. 0db
7 controlling protocol control of the functions and levels within the FX806A plmr audio processor is by a group of address/commands and appended data instructions from the system m controller to set/adjust the functions and elements of the FX806A. the use of these instructions is detailed in the following paragraphs and tables. control bits transmitted first audio output (rx) disabled enabled modulation drives disabled enabled pre-emphasis by-pass enabled input select rx audio in mic. in input level set input amp disabled -4.0db -3.0db -2.0db -1.0db 0db 1.0db 2.0db 3.0db 4.0db 5.0db 6.0db 7.0db 8.0db 9.0db 10.0db setting msb bit 7 0 1 6 0 1 5 0 1 4 0 1 32 10 00 00 00 01 00 10 00 11 01 00 01 01 01 10 01 11 10 00 10 01 10 10 10 11 11 00 11 01 11 10 11 11 mode bits transmitted first drive source signals calibration deviation limiter disabled enabled vogad disabled enabled de-emphasis enabled by-passed signal select internal external process gain set -4.0db -3.0db -2.0db 1.0db 0db 1.0db 2.0db 3.0db setting msb bit 7 0 1 6 0 1 5 0 1 4 0 1 3 0 1 210 000 001 010 011 100 101 110 111 control command (preceded by a/c 10 h ) table 2 control commands table 3 mode commands mode command (preceded by a/c 11 h ) command address/command (a/c) byte command table assignment hex binary data msb lsb general reset 01 0 0 0 0 0001 control command 10 0 0 0 1 0000 + 1 byte 2 mode command 11 0 0 0 1 0001 + 1 byte 3 mod. levels set 12 0 0 0 1 0010 + 2 bytes 4 volume set 13 0 0 0 1 0011 + 1 byte 5 table 1 c-bus address/commands in c-bus protocol the FX806A is allocated address/ command (a/c) values 10 h to 13 h . c-bus command, mode, modulation and volume assignments and data requirements are given in table 1 and illustrated in figure 5 (main block diagram). each instruction consists of an address/command (a/c) byte followed by a data instruction formulated from the following tables. commands and data are only to be loaded in the group configurations detailed, as the c-bus interface recognises the first byte after chip select (logic 0) as an address/ command. function or level control data, which is detailed in tables 2, 3, 4 and 5, is acted upon at the end of the loaded instruction. upon power-up the value of the bits in this device will be random (either 0 or 1). a general reset command (01 h ) will be required. this command is provided to reset all devices on the c-bus and has the following effect on the FX806A. control address command loaded as 00 h mode address command loaded as 00 h volume set loaded as 00 h
8 setting byte 1 msb 76 5 00 0 43210 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 byte 0 msb 76 5 00 0 43210 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 volume set transmitted first main process out enabled biased powersave chip enabled powersaved volume set attenuation off 48.0db 46.4db 44.8db 43.2db 41.6db 40.0db 38.4db 36.8db 35.2db 33.6db 32.0db 30.4db 28.8db 27.2db 25.6db 24.0db 22.4db 20.8db 19.2db 17.6db 16.0db 14.4db 12.8db 11.2db 9.6db 8.0db 6.4db 4.8db 3.2db 1.6db 0db setting msb 76 00 01 5 0 1 43210 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 table 4 modulator drive levels modulator levels (preceded by a/c12 h ) modulator drives first byte for transmission must be 0 mod. 1 attenuation 12.4db 12.0db 11.6db 11.2db 10.8db 10.4db 10.0db 9.6db 9.2db 8.8db 8.4db 8.0db 7.6db 7.2db 6.8db 6.4db 6.0db 5.6db 5.2db 4.8db 4.4db 4.0db 3.6db 3.2db 2.8db 2.4db 2.0db 1.6db 1.2db 0.8db 0.4db 0db last byte for transmission must be 0 mod. 2 attenuation 6.2db 6.0db 5.8db 5.6db 5.4db 5.2db 5.0db 4.8db 4.6db 4.4db 4.2db 4.0db 3.8db 3.6db 3.4db 3.2db 3.0db 2.8db 2.6db 2.4db 2.2db 2.0db 1.8db 1.6db 1.4db 1.2db 1.0db 0.8db 0.6db 0.4db 0.2db 0db volume set (preceded by a/c13 h ) table 5 volume set command loading address/commands and data bytes must be loaded in accordance with the information given in figure 6 (timing ). the powersave function is instigated by bit 5 of the volume set command (table 5). during powersave, all internal elements except the clock generator and c-bus interface are off, with the mic op- amp and output drive stage outputs connected to v ss . modulator drives are controlled separately, but the whole two-byte modulator drive command must be loaded for each required adjustment. chip select must be held at a logic 1 for the period t csoff between transactions.
9 command loading and timing to assist in rapid setting, the quick-reference guide below should be used together with figure 5. modulator levels a/c = 12 h byte 1 bit 7 C 5 0 4 C 0 mod 1 attenuation (0 to 12.4db) byte 2 7 C 5 0 4 C 0 mod 2 attenuation (0 to 6.2db) volume set a/c = 13 h bit 7 C 6 0 5 powersave 4 C 0 volume set attenuation (0 to 48db) control a/c = 10 h bit 7 audio out (rx) enable 6 modulator drive enable 5 pre-emphasis enable 4 input select (rx/tx) 3 C 0 input level set (-4db to 10db) mode a/c = 11 h bit 7 drive source 6 deviation limiter enable 5 vogad enable 4 de-emphasis enable 3 signal select 2 C 0 process gain set (-4db to 3db) table 6 quick-reference to command allocations parameter min. typ. max. unit t cse 2.0 C C m s t csh 4.0 C C m s t csoff 2.0 C C m s t nxt 4.0 C C m s t ck 2.0 C C m s notes (1) command data is transmitted to the peripheral msb (bit7) first, lsb (bit0) last. (2) data is clocked into the peripheral on the rising clock edge. (3) loaded data instructions are acted upon at the end of each individual, loaded byte. (4) to allow for differing m controller serial interface formats, the FX806A will work with either polarity serial clock pulses. msb general reset msb control command lsb lsb lsb volume set msb lsb modulator levels set msb 76543210 76543210 76543210 76543210 1 data byte 1 data byte 2 data bytes C byte 1 (loaded first) byte 0 (loaded last) table 2 table 3 table 5 table 4 sets the control, mode and volume commands to 00 h lsb mode command msb 76543210 1 data byte fig.7 examples of command data configurations serial clock command data t cse t nxt t nxt t csoff t csh address/command byte first data byte last data byte 76543210 76543210 76543210 msb lsb inter-byte period logic level is not important. chip select t ck fig.6 c-bus timing information
10 specification absolute maximum ratings exceeding the maximum rating can result in device damage. operation of the device outside the operating limits is not implied. supply voltage -0.3 to 7.0v input voltage at any pin (ref v ss = 0v) -0.3 to (v dd + 0.3v) sink/source current (supply pins) +/- 30ma (other pins) +/- 20ma total device dissipation @ t amb 25 c 800mw max. derating 10mw/ c operating temperature range: FX806A j -40 c to +85 c (cerdip) FX806A lg/ls -40 c to +85 c (plastic) storage temperature range: FX806A j -55 c to +125 c (cerdip) FX806A lg/ls -40 c to +85 c (plastic) operating limits all device characteristics are measured under the following conditions unless otherwise specified: v dd = 5.0v. t amb = 25 c. xtal/clock f 0 = 4.0mhz. audio level 0db ref: = 308mvrms @ 1khz (60% deviation, fm) . characteristics see note min. typ. max. unit static values supply voltage 4.5 5.0 5.5 v supply current (all elements enabled) C 8.0 C ma (maximum powersave) C 0.7 C ma c-bus interface input logic 1 3.5 C C v input logic 0 C C 1.5 v input leakage current (logic 1 or 0) -1.0 C 1.0 m a input capacitance C C 7.5 pf dynamic values overall performance microphone input 4, 5 C 25.0 C mvrms rx audio in 6, 5 154 C 308 mvrms output drive levels for 60% deviation 5, 7 291 308 326 mvrms for 100% deviation 5, 7, 8 C 1,440 C mv p - p passband frequencies 1 297 C 3000 hz passband ripple 2 -2.0 0.5 db stopband attenuation 1, 3 f = 150hz 10.0 12.0 C db f = 3400hz C 2.0 C db f = 6000hz 30.0 36.0 C db f = 8000hz to 20,000hz C 60.0 C db signal path noise rx 11 C -60.0 C dbp rx 10 C -55.0 C db tx 11 C -50.0 C dbp tx 10 C -45.0 C db distortion C 1.0 C % circuit elements C figure 5 mic amp or mod summation amp open loop gain C 50.0 C db bandwidth 20.0 C C khz input impedance 10.0 C C m w output impedance (open loop) C 6.0 C k w (closed loop) C 600 C w de-emphasis slope C -6.0 C db/oct. gain (at 1.0khz) C 0 C db input impedance C 500 C k w voltage controlled gain amp gain (non-compressing) 5 C 6.0 C db (full compression) C -24.0 C db vogad in input impedance C 10.0 C m w
11 specification ...... characteristics see note min. typ. max. unit vogad peak detectors output impedance - logic 1 (compress) C 1.0 C k w - logic 0 C 10.0 C m w hi/lo peak detector thresholds C 1,300 C mv p - p hi peak detector threshold C 650 C mv +ve pk input (low + highpass) filter gain (at 1.0khz) -1.0 0 1.0 db input level amp nominal adjustment range -4.0 10.0 db error of any setting -1.0 C 1.0 db step size 0.75 1.0 1.25 db external audio buffer gain -0.1 0 0.1 db pre-emphasis (main process and vogad) slope C 6.0 C db/oct. gain (at 1.0khz) C 10.0 C db process highpass filter gain (at 1.0khz) -1.0 0 1.0 db deviation limiter threshold C 1,300 C mv p - p gain -0.5 C 0.5 db process lowpass filter gain (at 1.0khz) -1.0 0 1.0 db process gain amp nominal adjustment range -4.0 3.0 db error of any setting -0.5 C 0.5 db step size 0.75 1.0 1.25 db output impedance C 600 C w transmitter modulator drives input impedance C 15.0 C k w mod.1 attenuator nominal adjustment range 0 12.4 db error of any setting -1.0 C 1.0 db step size 0.2 0.4 0.6 db output impedance C 600 C w mod.2 attenuator nominal adjustment range 0 6.2 db error of any setting -0.6 C 0.6 db step size 0.1 0.2 0.3 db output impedance C 600 C w audio output attenuator nominal adjustment range 0 48.0 db error of any setting -1.5 C 1.5 db step size C 1.6 C db output impedance C 600 C w miscellaneous impedances processed audio input C 500 C k w calibration input C 500 C k w external process out C 100 C w rx with de-emphasis by-pass C 25.0 C k w notes 1. between mic. or rx inputs to modulator or audio outputs. 2. the deviation from the ideal overall response that includes the pre- or de-emphasis slope. 3. excluding the effect of the pre- or de-emphasis slope. 4. producing an output of 0db with the mic. op-amp set to 6db (as shown in figure 2) and the modulator drives set to 0db. 5. with output drives set to 0db and the system calibrated, as described in the application pages. 6. input level range for 0db output, by adjustment of the input level amp. 7. it is recommended that these output levels will produce 60% or 100% deviation in the transmitter. 8. with the microphone input level 20db above the level required to produce 0db at the output drives. 9. using external components recommended in figure 2. 10. in a 30khz bandwidth. 11. dbp = psophometrically weighted measurement.
handling precautions the FX806A is a cmos lsi circuit which includes input protection. however precautions should be taken to prevent static discharges which may cause damage. cml does not assume any responsibility for the use of any circuitry described. no circuit patent licences are implied and cml reserves the right at any time without notice to change the said circuitry. package outlines the FX806A is available in the package styles outlined below. mechanical package diagrams and specifications are detailed in section 10 of this document. pin 1 identification marking is shown on the relevant diagram and pins on all package styles number anti-clockwise when viewed from the top. not to scale max. body length 10.25mm max. body width 10.25mm FX806A lg 24-pin quad plastic encapsulated bent and cropped (l1) FX806A j 24-pin cerdip dil (j4) not to scale max. body length 10.40mm max. body width 10.40mm FX806A ls 24-lead plastic leaded chip carrier (l2) not to scale max. body length 32.03mm max. body width 14.81mm ordering information FX806A j 24-pin cerdip dil (j4) FX806A lg 24-pin encapsulated bent and cropped (l1) FX806A ls 24-lead plastic leaded chip carrier (l2)

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